1. Field of the Invention
The present invention relates to a wafer-level test system and more particularly, to a wafer-level test module for testing image sensor chips of an integrated circuit wafer. The invention relates also to a wafer-level test method of image sensor chips using the wafer-level test module.
2. Description of the Related Art
Electronic devices fabrication must proceed some steps of test engineering respectively corresponding to the specific processing steps, especially for package-level test engineering after the wafer-level manufacturing and product test engineering before the final product modularization. Under the severe market competition, every manufactory emphasizes high-performance wafer-level test methods to effectively save packaging process for package-level test and control the quality of main process steps. Therefore, a complete wafer-level test system is an important test engineering to every manufactory.
A camera built inside the cell phone, PDA, leg-top computer, or any other portable electronic product is commonly formed of an image sensor module, which comprises a set of optical lens and an image sensor chip made subject to an integrated circuit process. When the set of optical lens projects the image on the image sensor chip, the circuit of the image sensor chip is operated to capture the image and store the image data in the portable electronic product. As a result, the electrical characteristics of the image sensor chip are highly photo-electronic related. Therefore, the wafer-level test engineering of an image sensor chip during the manufacturing process is important to the inspection of the electrical characteristics of the image sensor chip.
Even the wafer-level test on integrated circuit electronic devices has been well developed, when considering both the optical sensing technology and the circuit operation of the image sensor chip, there is still no any perfect wafer-level test system for testing multiple image sensor chips of an integrated circuit wafer accurately and rapidly. FIG. 1 illustrates a conventional test apparatus 1 of image sensor chips. This test apparatus 1 is comprised of a probe card 11 and a lens set 12. The lens set 12 is installed in the non-test circuit zone at the center of the probe card 11, and comprised of four optical lenses 120 and a lens mount 121. The lens mount 121 holds the optical lenses 120 in the probe card 11, allowing adjustment of every optical lens 120 to focus the incident light on a respective image sensor chip. The probe card 11 provides test signals to the respective image sensor chips then obtains each feedback test result from each of the image sensor chips respectively focused by the optical lenses 120. In view of the dimensional structure of an IC process, the dimension of one single optical lens 120 covers several image sensor chips in an integrated circuit wafer, however, only an image capturing device of the image sensor chip that is aligned with the optical axis of the respective optical lens 120 can receive an effective optical image, and the other circuit devices of the image sensor chip beyond the optical axis of the optical lens 120 cannot induce photo-electronic characteristics. As shown in FIG. 2, a standard integrated circuit wafer with 200 mm diameter has more than fifty or sixty unit chips. However, the lens set 12 simply covers a limited number of the unit chips (X-marked blocks in FIG. 2). Completing an electrical test engineering on the integrated circuit wafer which is integrated with image sensor chips needs to repeat more than ten times of the calibration procedure to align the optical axis of every optical lens 120 with an image capturing device of the respective image sensor chip. This test procedure is not a time-effective method. Further, it is difficult to control the optical precision when making optical axis alignment of the relatively larger size of the optical lenses 120 with the microsized image capturing devices of the corresponding image sensor chips.